Heinz Riener

Researcher, EPFL, Lausanne, Switzerland


Publications

Preprints

  • Roderick Bloem, Hana Chockler, Masoud Ebrahimi, Dana Fisman, Heinz Riener, Safety Synthesis Sans Specification, arXiv:2011.07630, subject: cs.FL, cs.LG, November, 2020. (arXiv) Preprint #6
  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli, Simulation-Guided Boolean Resubstitution, arXiv:2007.02579, subject: cs.LO, July, 2020. (arXiv) Preprint #5
  • Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Koenighofer, Ingo Pill, Heinz Riener, Franz Roeck, Synthesizing Test Strategies from Temporal Logic Specifications, arXiv:1809.01607, subject: cs.SE, cs.LO, September, 2018. (arXiv, PARTYStrategy) Preprint #4
  • Heinz Riener, Rüdiger Ehlers, Bruno Schmitt, Giovanni De Micheli, Exact Synthesis of ESOP Forms, arXiv:1807.11103, subject: cs.LO, July, 2018. (arXiv, GitHub, Benchmarks) Preprint #3
  • Mathias Soeken, Heinz Riener, Winston Haaswijk, Eleonora Testa, Bruno Schmitt, Giulia Meuli, Fereshte Mozafari, Giovanni De Micheli, The EPFL Logic Synthesis Libraries, arXiv:1805.05121v2, subject: cs.LO, cs.MS, submitted May, 2018, revised Novemeber 2019. (arXiv, GitHub) Preprint #2
  • Heinz Riener, Rüdiger Ehlers, Görschwin Fey, Path-Based Program Repair, arXiv:1503.04378, subject: cs.PL, cs.SE, March, 2015. (arXiv) Preprint #1

Journal Articles

  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Giovanni De Micheli, A Simulation-Guided Paradigm for Logic Synthesis and Verification, In Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, In press. (IEEE) Journal Article #6
  • Fereshte Mozafari, Heinz Riener, Mathias Soeken, Giovanni De Micheli, Efficient Boolean Methods for Preparing Uniform Quantum States, In Transactions on Quantum Engineering, volume 2, IEEE, 2021. (IEEE) Journal Article #5
  • Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Three-Input Gates for Logic Synthesis, In Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(10), IEEE, pp. 2184-2188, 2021. (IEEE) Journal Article #4
  • Mathias Soeken, Giulia Meuli, Bruno Schmitt, Fereshte Mozafari, Heinz Riener, Giovanni De Micheli, Boolean satisfiability in quantum compilation, In Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, 378(2164), Royal Society, 2019. (Royal Society) Journal Article #3
  • Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Koenighofer, Ingo Pill, Heinz Riener, Franz Roeck, Synthesizing Test Strategies from Temporal Logic Specifications, In Formal Methods in System Design, 55(2), Springer, pp. 103-135, 2019. (Springer) Journal Article #2
  • Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Göschwin Fey, metaSMT: Focus on Your Application and not on Solver Integration, In Journal on Software Tools for Technology Transfer (STTT) 19(5), Springer, pp. 605-621, 2017. (Springer, ACM Dig. Lib., GitHub) Journal Article #1

Book Chapters

  • Heinz Riener, Rüdiger Ehlers, Bruno de O. Schmitt, Giovanni De Micheli, Exact Synthesis of ESOP Forms, In Advanced Boolean Techniques, Springer, pp. 177-194, 2019. (Springer)
  • Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao, Designing Reliable Cyber-Physical Systems, In Languages, Design Methods, and Tools for Electronic System Design, vol. 454, Springer, pp. 15-38, 2018. (Springer)

Conference Papers

  • NEW Siang-Yun Lee, Heinz Riener, Giovanni De Micheli, Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition, In IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Virtual Conference, 2021. Conference Paper #26
  • NEW Bruno Schmitt, Fereshte Mozafari, Giulia Meuli, Heinz Riener, Giovanni De Micheli, From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++, In Design, Automation and Test in Europe (DATE), Virtual Conference, 2021. Conference Paper #25
  • NEW Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies, In Design, Automation and Test in Europe (DATE), Virtual Conference, 2021. Conference Paper #24
  • NEW Eleonora Testa, Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli, Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits, In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo Odaiba Waterfront, (Virtual conference), Japan, 2021. Conference Paper #23
  • Gianluca Martino, Heinz Riener, and Görschwin Fey, Revisiting Explicit Enumeration for Exact Synthesis, In Euromicro Conference on Digital System Design (DSD), Portoro┼ż, Slovenia, (Virtual conference), 2020. Conference Paper #22
  • Fereshte Mozafari, Mathias Soeken, Heinz Riener, Giovanni De Micheli, Automatic uniform quantum state preparation using decision diagrams, In International Symposium on Multiple-Valued Logic (ISMVL), Miyazaki, Japan, (Virtual conference), 2020. Conference Paper #21
  • Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener, Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle, In Design, Automation and Test in Europe (DATE), Grenoble, France, (Virtual conference), 2020. Conference Paper #20
  • Heinz Riener, Alan Mishchenko, Mathias Soeken, Exact DAG-aware rewriting, In Design, Automation and Test in Europe (DATE), Grenoble, France, (Virtual conference), 2020. Conference Paper #19
  • Eleonora Testa, Mathias Soeken, Heinz Riener, Luca Gaetano Amaru, Giovanni De Micheli, A logic synthesis toolbox for reducing the multiplicative complexity in logic networks, In Design, Automation and Test in Europe (DATE), Grenoble, France, (Virtual conference), 2020. Conference Paper #18
  • Heinz Riener, Exact synthesis of LTL properties from traces, In 2019 Forum on Specification and Design Languages (FDL), Southampton, UK, 2019. Conference Paper #17
  • Giulia Meuli, Bruno Schmitt, Rüdiger Ehlers, Heinz Riener, Giovanni De Micheli, Evaluating ESOP Optimization Methods in Quantum Compilation Flows, In Reversible Computation (RC), Lausanne, Switzerland, 2019. Conference Paper #16
  • Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca Amaru, Giovanni De Micheli, Mathias Soeken, Scalable Generic Logic Synthesis: One Approach to Rule Them All, In Design Automation Conference (DAC), pp. 70:1--70:6, Las Vegas, NV, US, 2019. (ACM Dig. Lib., PDF, GitHub, Experiments) Conference Paper #15
  • Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken, On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis, In Design, Automation and Test in Europe (DATE), pp. 1649-1654, Florence, Italy, 2019. (IEEEXplore, PDF) Conference Paper #14
  • Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener, Design Understanding: From Logic to Specification (special session), In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 172-175, Verona, Italy, 2018. (IEEEXplore, PDF) Conference Paper #13
  • Heinz Riener, Eleonora Testa, Luca Amaru, Mathias Soeken, Giovanni De Micheli, Size Optimization of MIGs with an Application to QCA and STMG Technologies, In 14th IEEE / ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 157-162, Athens, Greece, 2018. (ACM Dig. Lib., PDF) Conference Paper #12
  • Cunxi Yu, Heinz Riener, Francesca Stradolini, Giovanni De Micheli, Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model, In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, 2018. (IEEEXplore) Conference Paper #11
  • Jan Malburg, Heinz Riener, Görschwin Fey, Mining Latency Guarantees for RTL Designs, In 48th International Symposium on Multiple-Valued Logic (ISMVL), Linz, Austria, 2018. (IEEEXplore) Conference Paper #10
  • Heinz Riener, Rüdiger Ehlers, Görschwin Fey, CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification, In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256, Tokyo, Japan, 2017. (IEEEXplore, PDF) Conference Paper #9
  • Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao, Designing Reliable Cyber-Physical Systems (special session), In 2016 Forum on Specification and Design Languages (FDL), pp. 1-8, Bremen, Germany, 2016. (IEEEXplore) Conference Paper #8
  • Heinz Riener, Görschwin Fey, Exact Diagnosis Using Boolean Satisfiability, In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, 2016. (IEEEXplore, ACM Dig. Lib.) Conference Paper #7
  • Niels Thols, Heinz Riener, Görschwin Fey, Equivalence Checking on ESL Utilizing A Priori Knowledge, In Forum on Specification and Design Languages (FDL), pp. 1-8, Bremen, Germany, 2016. (IEEEXplore) Conference Paper #6
  • Niklas Krafczyk, Heinz Riener, Görschwin Fey, WCET Overapproximation for Software in the Context of a Cyber-Physical System, In IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6, Tallinn, Estonia, 2016. (IEEEXplore) Conference Paper #5
  • Niels Thols, Heinz Riener, Görschwin Fey, Equivalence Checking on System Level Using A Priori Knowledge, In IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 177-182, Belgrade, Serbia, 2015. (IEEEXplore, ACM Dig. Lib.) Conference Paper #4
  • Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler, metaSMT: A Unified Interface to SMT-LIB2, In 2014 Forum on Specification and Design Languages (FDL), pp. 1-6, Munich, Germany, 2014. (IEEEXplore) Conference Paper #3
  • Heinz Riener, Stefan Frehse, Görschwin Fey, Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis, In Design, Automation and Test in Europe (DATE), pp. 939-942, Grenoble, France, 2013. (IEEEXplore) Conference Paper #2
  • Heinz Riener, Görschwin Fey, Model-based Diagnosis versus Error Explanation, In Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), pp. 43--52, Arlington, VA, USA, 2012. (IEEEXplore) Conference Paper #1

Workshop Papers

  • Heinz Riener, Siang-Yun Lee, Alan Mishchenko, and Giovanni De Micheli, Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis, In 30th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2021.
  • Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, and Giovanni De Micheli, From Logic to Gates: A Versatile Mapping Approach to Restructure Logic, In 30th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2021.
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Michel Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits, In 30th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2021.
  • Dewmini Sudara Marakkalage, Heinz Riener, and Giovanni De Micheli, Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using Exact Methods, In 30th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2021.
  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert Brayton, Giovanni De Micheli, Simulation-Guided Boolean Resubstitution, In 29th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2020. (arXiv)
  • Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Three-Input Gates for Logic Synthesis, In 29th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2020.
  • Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies, In 29th International Workshop on Logic & Synthesis (IWLS), Virtual Conference, 2020.
  • Heinz Riener, Mathias Soeken, Eleonora Testa, Giovanni De Micheli, Generic Logic Synthesis meets RTL Synthesis, In Workshop on Open-Source EDA Technology (WOSET), Westminster, CO, USA, 2019.
  • Gianluca Martino, Heinz Riener, Görschwin Fey, Complete Specification Mining, In 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Florence, Italy, 2019. (PDF)
  • Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca Amaru, Giovanni De Micheli, Mathias Soeken, Logic Optimization of Majority-Inverter Graphs, In 22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), Kaiserslautern, Germany, 2019. (IEEEXplore, PDF)
  • Giulia Meuli, Bruno De O. Schmitt, Heinz Riener, Giovanni De Micheli, SAT-based Optimal ESOP Synthesis, In International Workshop on Quantum Compilation (IWQC), San Diego, CA, USA, 2018.
  • Mathias Soeken, Heinz Riener, Winston Haaswijk, Eleonora Testa, Giovanni De Micheli, The EPFL Logic Synthesis Libraries, In Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, USA, 2018.
  • Heinz Riener, Rüdiger Ehlers, Bruno Schmitt, Giovanni De Micheli, Exact Synthesis of ESOP Forms, In 13th International Workshop on Boolean Problems (IWSBP), Bremen, Germany, 2018. (GitHub, Benchmarks)
  • Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De Micheli, The EPFL Logic Synthesis Libraries, In 27th International Workshop on Logic & Synthesis (IWLS), San Francisco, CA, USA, 2018. (GitHub)
  • Gianluca Martino, Heinz Riener, Görschwin Fey, Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems, In 27th International Workshop on Logic & Synthesis (IWLS), San Francisco, CA, USA, 2018. (GitHub)
  • Jan Malburg, Heinz Riener, Görschwin Fey, Mining Latency Guarantees for RT-level Designs, In 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Lausanne, Switzerland, 2017.
  • Heinz Riener, Görschwin Fey, Computing Exact Fault Candidates Incrementally, In 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Lausanne, Switzerland, 2017.
  • Heinz Riener, Rüdiger Ehlers, Görschwin Fey, Counterexample-Guided EF Synthesis of Boolean Functions, In 20th Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), pp. 67-74, Bremen, Germany, 2017. (Shaker, PDF)
  • Heinz Riener, Görschwin Fey, Counterexample-Guided Diagnosis, In 1st IEEE International Verification and Security Workshop (IVSW), pp. 1-6, Sant Feliu de Guixols, Catalunya, Spain, 2016. (IEEEXplore)
  • Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem, SMT-Based CPS Parameter Synthesis, In Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek 2016), vol 43, pp. 126-133, Vienna, Austra, 2016. (Easychair proc., GitHub)
  • Heinz Riener, Rüdiger Ehlers, Görschwin Fey, Path-Based Program Repair, In 12th International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS, pp. 22-32, London, United Kingdoms, 2015. (EPTCS proc.)
  • Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey, A Logic for Cardinality Constraints (extended abstract), In 16th Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), pp. 217-220, Böblingen, Germany, 2014.
  • Heinz Riener, Görschwin Fey, Yet a Better Error Explanation Algorithm, In 15th Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), pp. 193-194, Warnem¨nde, Germany, 2013.
  • Heinz Riener, Görschwin Fey, FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation, In 19th International Workshop on Model Checking Software (SPIN), pp. 234-240, Oxford, UK, 2012. (Springer)
  • Heinz Riener, Roderick Bloem, Görschwin Fey, Test Case Generation from Mutants Using Model Checking Techniques, In Fourth IEEE International Conference on Software Testing, Verification and Validation (ICST Workshops), pp. 388-397, Berlin, Germany, 2011. (IEEEXplore)

Contact

Heinz Riener
EPFL IC ISIM LSI1
INF 333, Station 14
1015 Lausanne, Switzerland

+41 21 69 30914
heinz.riener@gmail.com
GitHub
DBLP
ORCID
SCOPUS
LinkedIn