Heinz Riener

Researcher, EPFL, Lausanne, Switzerland


Projects

  • Open Logic Synthesis Libraries and Benchmarks

    The Integrated Systems Laboratory (LSI) at EPFL develops a collection of open software libraries and benchmarks to keep up the driving force in improving optimization algorithms in the field of logic synthesis. The developed open science infrastructure can be used to tackle complex research problems.

    The Open Logic Synthesis Libraries and Benchmarks project focuses on building up an active open source community in the field of logic synthesis beyond EPPL with an emphasis on open reproducible and comparable experimental results through open software and benchmarks. The objectives are (1) to extend the community around the EPFL Logic Synthesis Libraries and EPFL Logic Synthesis Benchmarks beyond EPFL, (2) to support researchers from academia and industry to contribute and use the developed software infrastructure, and (3) to work out an open development methodology that shares the experiences and best practices gathered at EPFL in developing open libraries and benchmarks for logic synthesis. We believe that this project enables high quality research and improves research efficiency and collaboration in logic synthesis and beyond.

    Start: July, 2019 (1.5 years)

    Role: Principal Investigator (Co-PI in cooperation with Prof. Giovanni De Micheli, EPFL, Switzerland)

    Further information:
    EPFL Logic Synthesis Libraries: https://github.com/lsils/lstools-showcase
    EPFL Logic Synthesis Benchmarks: https://github.com/lsils/benchmarks

Program Committees

  • NEW Design Automation Conference (DAC) 2022, San Francisco, CA, USA, July 10-14, 2022. (Link)
  • NEW 25th Design, Automation, and Test in Europe (DATE) conference, Antwerb, Belgium, March 14-23, 2022. (Link)
  • Forum on Specification & Design Languages (FDL), Antibes, France, September 8-10, 2021. (Link)
  • International Workshop on Logic & Synthesis (IWLS) 2021, Virtual Conference, July 19-22, 2021. (Link)
  • Design Automation Conference (DAC) 2021, San Francisco, CA, USA, December 5-9, 2021. (Link)
  • 24th Design, Automation, and Test in Europe (DATE) conference, Grenoble, France, February 1-5, 2021. (Link)
  • International Workshop on Boolean Problems (IWSBP) 2020, Bremen, Germany, September 24-25, 2020. (Link)
  • International Workshop on Logic & Synthesis (IWLS) 2020, Virtual Conference, USA, July 18-19, 2020. (Link)
  • Design Automation Conference (DAC) 2020, San Francisco, CA, USA, July 19-23, 2020. (Link)
  • 23rd Design, Automation, and Test in Europe (DATE) conference, Grenoble, France, March 9-13, 2020. (Link)
  • 1st IEEE International Verification and Security Workshop (IVSW), Rhodes Island, Greece, July 1-3, 2019. (Link)
  • Special Session on Future Trends in Emerging Technologies (FTET) at the Euromicro Conference on Digital System Design, Kallithea, Chalkidiki, Greece, August 28-30, 2019. (Link)
  • 37th IEEE International Conference on Computer Design, Abu Dhabi, UAE, November 17-20, 2019. (Link)
  • 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Florence, Italy, March 29, 2019. (Link)
  • 3rd IEEE International Verification and Security Workshop (IVSW), Platja d’Aro, Costa Brava, Spain, July 2-4, 2018. (Link)
  • 2nd IEEE International Verification and Security Workshop (IVSW), Thessaloniki, Greece, July 3-5, 2017. (Link)
  • 1st IEEE International Verification and Security Workshop (IVSW), Sant Feliu de Guixols, Catalunya, Spain, July 4-6, 2016. (Link)

Invited Talks & Presentations

2021

  • NEW July 2021, Virtual: The EPFL Logic Synthesis Libraries in Action: A Development Snapshot of mockturtle & tweedledum. Joined presentation with Bruno Schmitt in the 2nd Logic Synthesis Software School (LSSS) co-organized with International Workshop on Logic & Synthesis (IWLS)
  • NEW March 2021, Cadence Design Systems Inc., Virtual: mockturtle: a C++ logic network library

2019

  • October 2020, Virtual Conference: mockturtle: a logic network library in Fifth CROSS Research Symposium organized by Prof. Jose Renau (More information)
  • February 2020, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, US: EPFL Logic Synthesis Libraries Revisited invited by Victor N. Kravets
  • September 2019, Brno, Czech Republic: SAT-based Exact Synthesis at the 13th Alpine Verification Meeting (AVM'19) (More information)
  • August 2019, Graz University of Technology, Austria: Modern Tools for Logic Synthesis invited by Prof. Roderick Bloem (More information)
  • June 2019, Lausanne, Switzerland: The EPFL Logic Synthesis Lirbaries in the Logic Synthesis Software School (More information)
  • June 2019, Zurich, Switzerland: Design Automation in Wonderland: The EPFL Logic Synthesis Lirbaries in the Week of Open Source Hardware (More information)
  • June 2019, Las Vegas, NV, US: The EPFL Logic Synthesis Libraries in Birds-of-a-Feather Meeting: Open-Source Academic EDA Software Continued organized by Prof. Andrew Kahng (More information)

2018

  • September 2018, Hamburg University of Technology, Germany: Size Optimization of Majority-Inverter Graphs with an Application to QCA and STMG Technologies invited by Prof. Görschwin Fey (More information)

2017

  • May 2017, Graz University of Technology, Austria: Exact Diagnosis using Boolean Satisfiability invited by Prof. Roderick Bloem
  • February 2017, EPFL, Lausanne, Switzerland: CEGAR-based EF Synthesis of Boolean functions with an Application to Circuit Rectification invited by Prof. Giovanni De Micheli (More information)

2016 and earlier

  • April 2016, ARTEMIS Industrial Association, Vienna, Austria: Immortalizing Many-Core Based Cyber-Physical Systems (More information)
  • December 2012, Duke Univeristy, Durham, NC, USA: Test Case Generation from Mutants using Model Checking Techniques invited by Prof. Krishnendu Chakrabarty (More information)

Collaborators

Contact

Heinz Riener
EPFL IC ISIM LSI1
INF 333, Station 14
1015 Lausanne, Switzerland

+41 21 69 30914
heinz.riener@gmail.com
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